A verification test bench is developed to test an integrated circuit design and determine whether the integrated circuit design complies with the functional specification of the integrated circuit design. The design of an integrated circuit is a complex project that typically involves the cooperation of many teams of engineers. Between the start of planning the high-level architecture to taping out the low-level photomasks, the integrated circuit design undergoes successive back-and-forth iterations of developing the design, verifying the design, and fixing the design.
Verification methodology generally follows this iterative behavior of finding and fixing issues in the integrated circuit design. However, it is not always possible to have a complete verification test bench for verifying and fixing the integrated circuit design from inception. Therefore, a realistic verification methodology involves iteratively developing the verification test bench alongside the integrated circuit design while finding and fixing issues in the integrated circuit design.
It is desirable to develop and bring integrated circuit devices to market as quickly as possible. Therefore, it would be advantageous to accelerate the iterative process of developing a verification test bench alongside the integrated circuit development.